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4-bit single-chip microcontroller the m pd754304 is one of the 75xl series 4-bit single-chip microcontrollers with data processing capability comparable to that of 8-bit microcontrollers. the m pd754303(a) has a higher reliability than the m pd754304. the microcontrollers in the 75xl series have expanded cpu functions than those of the 75x series and can operate at a voltage of as low as 1.8 v; therefore, they are ideal for battery-driven application systems. as the one-time prom version of the m pd754304, the m pd75p4308 is ideal for evaluation of a system under development or for small-scale production of application systems. detailed information about functions can be found in the following document. be sure to read the following document before designing. m pd754304 users manual: u10123e features ? low-voltage operation: v dd = 1.8 to 5.5 v ? internal memory program memory (rom): 2048 8 bits ( m pd754302, 754302(a)) 4096 8 bits ( m pd754304, 754304(a)) data memory (ram): 256 4 bits applications ? m pd754302, 754302(a) cordless telephones, tvs, vcrs, audio systems, household appliances, office machines, etc. ? m pd754304, 754304(a) automotive appliance, etc. the m pd754302 and 754304 differ from the m pd754302(a) and 754304(a) only in terms of their quality grade. unless otherwise specified, the m pd754304 is treated as a representative model in this data sheet. for the models other than the m pd754304, m pd754304 can be read as the other model name. if different descriptions are made for the m pd754302 and 754304, the (a) models correspond as follows: m pd754302 ? m pd754302(a), m pd754304 ? m pd754304(a) mos integrated circuit the information in this document is subject to change without notice. document no. u10797ej2v0ds00 (2nd edition) date published november 1996 n printed in japan m pd754302,754304,754302(a),754304(a) ? variable instruction execution time effective for high- speed operation and power saving 0.95, 1.91, 3.81, or 15.3 m s (at 4.19 mhz) 0.67, 1.33, 2.67, or 10.7 m s (at 6.0 mhz) ? internal serial interface (1 channel) ? powerful timer function (3 channels) ? inherits instruction set of existing 75x series for easy replacement the mark shows major revised points. 1996 data sheet
m pd754302, 754304, 754302(a), 754304(a) 2 ordering information parts number package quality grade m pd754302gs- 36-pin plastic shrink sop (300 mil, 0.8 mm pitch) standard m pd754304gs- 36-pin plastic shrink sop (300 mil, 0.8 mm pitch) standard m pd754302gs(a)- 36-pin plastic shrink sop (300 mil, 0.8 mm pitch) special m pd754304gs(a)- 36-pin plastic shrink sop (300 mil, 0.8 mm pitch) special remark indicates a rom code number. difference between m pd75430 and m pd75430 (a) parts number m pd754302 m pd754302(a) item m pd754304 m pd754304(a) quality grade standard special please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
m pd754302, 754304, 754302(a), 754304(a) 3 functional outline parameter function instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (@ 4.19 mhz with system clock) ? 0.67, 1.33, 2.67, 10.7 m s (@ 6.0 mhz with system clock) on-chip memory rom 2048 8 bits ( m pd754302) 4096 8 bits ( m pd754304) ram 256 4 bits general-purpose register ? 4-bit operation: 8 4 banks ? 8-bit operation: 4 4 banks input/ cmos input 8 on-chip pull-up resistors can be specified by software: 7 output cmos input/output 18 on-chip pull-up resistors can be specified by software: 18 port n-ch open-drain 4 13 v withstand voltage. on-chip pull-up resistors can be specified by input/output pins mask option. total 30 timer 3 channels ? 8-bit timer/event counter: 2 channels (16-bit timer/event counter) ? basic interval timer/watchdog timer: 1 channel serial interface ? 3-wire serial i/o mode ... msb or lsb can be selected for transferring top bit ? 2-wire serial i/o mode bit sequential buffer 16 bits clock output (pcl) ? f , 524, 262, 65.5 khz (@ 4.19 mhz with system clock) ? f , 750, 375, 93.8 khz (@ 6.0 mhz with system clock) vectored interrupts external: 3, internal: 4 test input external: 1 system clock oscillator ceramic or crystal oscillator standby function stop/halt mode operating ambient t a = C40 to +85 ?c temperature power supply voltage v dd = 1.8 to 5.5 v package 36-pin plastic shrink sop (300 mil, 0.8-mm pitch)
m pd754302, 754304, 754302(a), 754304(a) 4 contents 1. pin configuration (top view) 6 2. block diagram 8 3. pin function 9 3.1 port pins 9 3.2 non-port pins 10 3.3 pin input/output circuits 11 3.4 recommended connections for unused pins 13 4. switching function between mk i mode and mk ii mode 14 4.1 difference between mk i and mk ii modes 14 4.2 setting method of stack bank select register (sbs) 15 5. memory configuration 16 6. peripheral hardware functions 20 6.1 digital input ports 20 6.2 clock generator 21 6.3 clock output circuit 22 6.4 basic interval timer/watchdog timer 23 6.5 timer/event counter 24 6.6 serial interface 27 6.7 bit sequential buffer 29 7. interrupt function and test function 30 8. standby function 32 9. reset function 33 10. mask option 36 11. instruction sets 37 12. electrical specifications 49 13. characteristics curves (reference values) 61 14. package drawing 63 15. recommended soldering conditions 64
m pd754302, 754304, 754302(a), 754304(a) 5 appendix a. comparison of functions among m pd750004, 754304, and 75p4308 65 appendix b. development tools 67 appendix c. related documents 70
m pd754302, 754304, 754302(a), 754304(a) 6 1. pin configuration (top view) 36-pin plastic shrink sop (300 mil, 0.8-mm pitch) m pd754302gs- , m pd754302gs(a)- m pd754304gs- , m pd754304gs(a)- ic: internally connected (connect directly this pin to v dd .) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 v ss x1 x2 reset p33 p32 p31 p30 p81 p80 p23 p22/pcl p21/pto1 p20/pto0 p03/si p02/so/sb0 p01/sck p00/int4 p50 p51 p52 p53 p60/kr0 p61/kr1 p62/kr2 p63/kr3 p70/kr4 p71/kr5 p72/kr6 p73/kr7 p13/ti0/ti1 p12/int2 p11/int1 p10/int0 v dd ic
m pd754302, 754304, 754302(a), 754304(a) 7 pin identification p00-p03 : port0 reset : reset input p10-p13 : port1 ti0, ti1 : timer input 0, 1 p20-p23 : port2 pto0, pto1: programmable timer output 0, 1 p30-p33 : port3 pcl : programmable clock p50-p53 : port5 int0, 1, 4 : external vectored interrupt 0, 1, 4 p60-p63 : port6 int2 : external test input 2 p70-p73 : port7 v ss : gnd p80, p81 : port8 x1, x2 : system clock oscillation 1, 2 kr0-kr7 : key return 0-7 ic : internally connected sck : serial clock v dd : positive power supply si : serial input so : serial output sb0 : serial data bus 0
m pd754302, 754304, 754302(a), 754304(a) 8 notes 1. the m pd754302 and m pd754304 program counters are 11 and 12 bits, respectively. 2. the rom capacity of the m pd754302 is 2048 8 bits, and that of the m pd754304 is 4096 8 bits. 2. block diagram general reg. ram data memory 256 4 bits sp (8) sbs bank decode and control rom note2 program memory program counter note1 alu stand by control cpu clock f clock generator clock divider clock output control pcl/p22 x1 x2 f x /2 n bit seq. buffer (16) port0 port1 port2 port3 port5 port6 port7 port8 4 4 4 4 4 4 4 2 4 4 4 4 4 4 4 2 p00-p03 p10-p13 p20-p23 p30-p33 p50-p53 p60-p63 p70-p73 p80, p81 basic interval timer/ watchdog timer intbt 8-bit timer/event counter#0 8-bit timer/event counter#1 cascaded 16-bit timer/ event counter intt1 intt0 tout0 ti0/ti1/p13 pto0/p20 pto1/p21 clocked serial interface si/p03 sck/p01 so/sb0/p02 intcsi tout0 interrupt control int0/p10 int2/p12 int1/p11 int4/p00 kr0-kr3/p60-p63 kr4-kr7/p70-p73 8 cy reset v ss v dd ic
m pd754302, 754304, 754302(a), 754304(a) 9 programmable 4-bit input/output port (port6). this port can be specified for input/output bit-wise. on-chip pull-up resistors can be specified by software in 4-bit units. 3. pin function 3.1 port pins pin name input/output alternate 8-bit after reset i/o circuit function i/o type note 1 p00 input int4 input b p01 input/output sck f -a p02 input/output so/sb0 f -b p03 input si b -c p10 input int0 input b -c p11 int1 p12 int2 p13 ti0/ti1 p20 input/output pto0 input e-b p21 pto1 p22 pcl p23 C p30 input/output C input e-b p31 C p32 C p33 C p50-p53 note 2 input/output C m-d p60 input/output kr0 ? input f -a p61 kr1 p62 kr2 p63 kr3 p70 input/output kr4 input f -a p71 kr5 p72 kr6 p73 kr7 p80 input/output C input e-b p81 C notes 1. circled characters indicate the schmitt-trigger input. 2. if on-chip pull-up resistors are not specified by mask option (when used as n-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. high level (when pull-up resistors are provided) or high- impedance function 4-bit input port (port0). for p01 to p03, on-chip pull-up resistors can be specified by software in 3-bit units. programmable 4-bit input/output port (port3). this port can be specified for input/output bit-wise. on-chip pull-up resistor can be specified by software in 4-bit units. 4-bit input/output port (port2). on-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input port (port1). on-chip pull-up resistors can be specified by software in 4-bit units. noise elimination circuit can be selected (only p10/int0) 4-bit input/output port (port7). on-chip pull-up resistors can be specified by software in 4-bit units. 2-bit input/output port (port8). on-chip pull-up resistors can be specified by software in 2-bit units. n-ch open-drain 4-bit input/output port (port5). a pull-up resistor can be contained bit-wise (mask option). withstand voltage is 13 v in open-drain mode.
m pd754302, 754304, 754302(a), 754304(a) 10 3.2 non-port pins pin name input/output alternate function after reset i/o circuit function type note ti0/ti1 input p13 inputs external event pulses to the timer/event input b -c counter. pto0 output p20 timer/event counter output input e-b pto1 p21 pcl p22 clock output sck input/output p01 serial clock input/output input f -a so/sb0 p02 serial data output f -b serial data bus input/output si input p03 serial data input b -c int4 input p00 edge detection vectored interrupt input (both input b rising edge and falling edge detection) int0 input p10 input b -c int1 p11 int2 input p12 input b -c kr0-kr3 input p60-p63 testable input (falling edge detection) input f -a kr4-kr7 p70-p73 x1 input C crystal/ceramic connection pin for the system C C clock oscillator. when inputting the external clock, input the external clock to pin x1, and x2 C the inverted phase of the external clock to pin x2. reset input C system reset input (low-level active) C b ic C C internally connected. connect directly to v dd .C C v dd C C positive power supply C C v ss C C ground potential C C note circled characters indicate the schmitt-trigger input. edge detection vectored asynchronous with interrupt input (detection noise elimination edge can be selected). circuit can be selected int0/p10 can select a noise elimination circuit. asynchronous edge detection testable asynchronous input (rising edge detection)
m pd754302, 754304, 754302(a), 754304(a) 11 3.3 pin input/output circuits the m pd754304 pin input/output circuits are shown schematically. type a type b type d type e-b type b-c type f-a v dd in p-ch n-ch data output disable n-ch p-ch in out v dd p-ch output disable data p.u.r. enable type d type a in/out v dd p.u.r. enable p.u.r. p-ch in v dd p.u.r. p.u.r. enable p-ch in/out type d type b output disable data p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor schmitt trigger input having hysteresis characteristic. cmos specification input buffer. push-pull output that can be placed in output high-impedance (both p-ch, n-ch off). p.u.r. v dd
m pd754302, 754304, 754302(a), 754304(a) 12 v dd p-ch n-ch in/out v dd p-ch p.u.r. p.u.r. enable output disable (p) data output disable output disable (n) p.u.r. : pull-up resistor type f-b type m-d p-ch v dd p.u.r. note in/out v dd data output disable p.u.r. : pull-up resistor p.u.r. (mask option) n-ch (+13 v) (+13 v) note voltage limiting circuit input instruction if this pull-up resistor is not connected using the mask option it operates only when the input instruction is executed (if the pin is low, current flows from v dd to the pin).
m pd754302, 754304, 754302(a), 754304(a) 13 3.4 recommended connections for unused pins table 3-1. list of recommended connections for unused pins pin recommended connection p00/int4 connect to v ss or v dd p01/sck connect to v ss or v dd through the resistor individually p02/so/sb0 p03/si connect to v ss p10/int0-p12/int2 connect to v ss or v dd p13/ti0/ti1 p20/pto0 input state : connect to v ss or v dd through the resistor p21/pto1 individually p22/pcl output state : leave open p23 p30-p33 p50-p53 input state : connect to v ss output state : connect to v ss (pull-up resistor by mask option should not be connected) p60/kr0-p63/kr3 input state : connect to v ss or v dd through the resistor p70/kr4-p73/kr7 individually p80, p81 output state : leave open ic connect to v dd directly
m pd754302, 754304, 754302(a), 754304(a) 14 4. switching function between mk i mode and mk ii mode 4.1 difference between mk i and mk ii modes the cpu of m pd754304 has the following two modes: mk i and mk ii, either of which can be selected. the mode can be switched by the bit 3 of the stack bank select register (sbs). ? mk i mode: can be used in the 75xl cpu with a rom capacity of up to 16k bytes. ? mk ii mode: can be used in all the 75xl cpus including those products whose rom capacity is more than 16k bytes. table 4-1. differences between mk i mode and mk ii mode mk i mode mk ii mode number of stack bytes 2 bytes 3 bytes for subroutine instructions bra !addr1 instruction not available available calla !addr1 instruction call !addr instruction 3 machine cycles 4 machine cycles callf !faddr instruction 2 machine cycles 3 machine cycles caution the mk ii mode supports a program area exceeding 16k bytes in the 75x and 75xl series. this mode can improve software compatibility with products with a program area of more than 16k bytes. when mk ii mode is selected, the number of stack bytes when a subroutine call instruction is executed is greater by 1 byte per stack compared with the mk i mode. when the call !addr or callf !faddr instruction is used, one more machine cycle is required. to emphasize the efficiency of the ram and processing speed rather than software compatibility, therefore, use the mk i mode.
m pd754302, 754304, 754302(a), 754304(a) 15 4.2 setting method of stack bank select register (sbs) switching between the mk i mode and mk ii mode can be done by the sbs. figure 4-1 shows the format. the sbs is set by a 4-bit memory manipulation instruction. when using the mk i mode, the sbs must be initialized to 1000b at the beginning of a program. when using the mk ii mode, it must be initialized to 0000b. figure 4-1. stack bank select register format caution since sbs. 3 is set to 1 after a reset signal is generated, the cpu operates in the mk i mode. when executing an instruction in the mk ii mode, set sbs. 3 to 0 to select the mk ii mode. sbs3 sbs2 sbs1 sbs0 3210 symbol sbs address f84h 00 0 1 0 memory bank 0 other than above setting prohibited 0 must be set in the bit 2 position. stack area specification mk ii mode mk i mode mode switching specification
m pd754302, 754304, 754302(a), 754304(a) 16 5. memory configuration program memory (rom) .... 2048 8 bits ( m pd754302) .... 4096 8 bits ( m pd754304) ? addresses 0000h and 0001h vector table wherein the program start address and the values set for the rbe and mbe at the time a reset signal is generated are written. reset and start are possible at an arbitrary address. ? addresses 0002h-000dh vector table wherein the program start address and values set for the rbe and mbe by the vectored interrupts are written. interrupt execution can be started at an arbitrary address. ? addresses 0020h-007fh table area referenced by the geti instruction note . note the geti instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. it is used to decrease the program steps. ? data memory (ram) ? data area .... 256 words 4 bits (000h-0ffh) ? peripheral hardware area .... 128 words 4 bits (f80h-fffh)
m pd754302, 754304, 754302(a), 754304(a) 17 figure 5-1. program memory map (1/2) (a) m pd754302 note can be used in the mk ii mode only. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction. 0000h address 7654 mbe rbe 0 0 internal reset start address (high-order 4 bits) 0 0002h mbe rbe 0 0 intbt/int4 (high-order 4 bits) start address 0004h mbe rbe 0 0 int0 (high-order 4 bits) start address 0006h mbe rbe 0 0 int1 (high-order 4 bits) start address 0008h mbe rbe 0 0 intcsi (high-order 4 bits) start address 000ah mbe rbe 0 0 intt0 (high-order 4 bits) start address 000ch mbe rbe 0 0 intt1 (high-order 4 bits) start address 0020h 007fh 0080h 07ffh geti instruction reference table (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf ! faddr instruction entry address call !addr instruction subroutine entry address br $addr instruction relative branch address _ 15 to _ 1, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed internal reset start address intbt/int4 start address int0 start address int1 start address intcsi start address intt0 start address intt1 start address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction
m pd754302, 754304, 754302(a), 754304(a) 18 figure 5-1. program memory map (2/2) (b) m pd754304 note can be used in the mk ii mode only. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction. 0000h address 7654 mbe rbe 0 0 internal reset start address (high-order 4 bits) 0 0002h mbe rbe 0 0 intbt/int4 (high-order 4 bits) start address 0004h mbe rbe 0 0 int0 (high-order 4 bits) start address 0006h mbe rbe 0 0 int1 (high-order 4 bits) start address 0008h mbe rbe 0 0 intcsi (high-order 4 bits) start address 000ah mbe rbe 0 0 intt0 (high-order 4 bits) start address 000ch mbe rbe 0 0 intt1 (high-order 4 bits) start address 0020h 007fh 0080h 07ffh 0800h 0fffh geti instruction reference table (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf ! faddr instruction entry address call !addr instruction subroutine entry address br $addr instruction relative branch address _ 15 to _ 1, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed internal reset start address intbt/int4 start address int0 start address int1 start address intcsi start address intt0 start address intt1 start address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction
m pd754302, 754304, 754302(a), 754304(a) 19 figure 5-2. data memory map data area static ram (256 4) stack area general-purpose register area 000h 01fh 0ffh f80h fffh peripheral hardware area data memory memory bank 0 (32 4) 256 4 (224 4) not incorporated 128 4 15
m pd754302, 754304, 754302(a), 754304(a) 20 6. peripheral hardware functions 6.1 digital input ports the following three types of i/o ports are provided. ? cmos input (ports 0, 1) : 8 ? cmos i/o (ports 2, 3, 6 to 8) : 18 ? n-ch open-drain i/o (port 5) : 4 total 30 table 6-1. types and features of digital ports port name function operation, features remark port0 4-bit input when serial interface function is used, multiplexed pin multiplexed with int4, sck, has output function depending on operation mode. so/sb0, and si pins port1 input port. multiplexed with int0 through int2 and ti0/ti1 pins. port2 4-bit i/o can be set in input or output mode in 4-bit units. multiplexed with pto0, pto1, and pcl pins. port3 can be set in input or output mode in 1-bit units. port5 4-bit i/o can be set in input or output mode in 4-bit units. pull-up (n-ch open- resistor can be connected in 1-bit units by mask option. drain, 13 v) port6 4-bit i/o can be set in input or ports 6 and 7 are used in multiplexed with kr0 through output mode in 1-bit units. pairs and can input or kr3 pins. port7 can be set in input or output data in 8-bit units. multiplexed with kr4 through output mode in 4-bit units. kr7 pins. port8 2-bit i/o can be set in input or output mode in 2-bit units.
m pd754302, 754304, 754302(a), 754304(a) 21 note instruction execution remarks 1. f x = system clock frequency 2. f = cpu clock 3. pcc: processor clock control register 4. one clock cycle (t cy ) of the cpu clock is equal to one machine cycle of the instruction. x1 x2 f x system clock oscillator 4 halt note stop note pcc0 pcc1 pcc2 pcc3 pcc2, pcc3 clear stop f/f q s r oscillation stop halt f/f s r wait signal from bt reset signal standby release signal from interrupt control circuit cpu int0 noise eliminator clock output circuit f 1/4 divider 1/1 to 1/4096 divider 1/2 1/4 1/16 basic interval timer (bt) timer/event counters 0, 1 serial interface int0 noise eliminator clock output circuit pcc q selector internal bus 6.2 clock generator ? clock generator configuration the clock generator provides the clock signals to the cpu and peripheral hardware and its configuration is shown in figure 6-1. the operation of the clock generator is set with the processor clock control register (pcc). the instruction execution time can be changed. ? 0.95, 1.91, 3.81, 15.3 m s (system clock operating at 4.19 mhz) ? 0.67, 1.33, 2.67, 10.7 m s (system clock operating at 6.0 mhz) figure 6-1. clock generator block diagram
m pd754302, 754304, 754302(a), 754304(a) 22 from clock generator f f x /2 3 f x /2 4 f x /2 6 selector clom3 0 clom1 clom0 4 clom p22 output latch port 2 i/o mode specification bit port2.2 bit 2 of pmgb internal bus output buffer pcl/p22 6.3 clock output circuit the clock output circuit outputs clock pulses from the p22/pcl pin, and is used to apply for remote controller waveform output or to supply clock pulse peripheral lsis. ? clock output (pcl) : f , 524, 262, 65.5 khz (during 4.19-mhz operation) f , 750, 375, 93.8 khz (during 6.0-mhz operation) figure 6-2. clock output circuit block diagram remark special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable.
m pd754302, 754304, 754302(a), 754304(a) 23 6.4 basic interval timer/watchdog timer the basic interval timer/watchdog timer has the following functions. ? interval timer operation to generate a reference time interrupt ? watchdog timer operation to detect a runaway of program and reset the cpu ? selects and counts the wait time when the standby mode is released ? reads the contents of counting figure 6-3. basic interval timer/watchdog timer block diagram from clock generator f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx btm3 btm2 btm1 btm0 btm 4 set1 note internal bus 81 basic interval timer (8-bit frequency divider) clear bt wait release signal when standby is released. set clear 3 wdtm set1 note internal reset signal vectored interrupt request signal bt interrupt request flag irqbt note instruction execution
m pd754302, 754304, 754302(a), 754304(a) 24 6.5 timer/event counter the m pd754304 has two channels of timer/event counters. its configuration is shown in figures 6-4 and 6-5. the timer/event counter has the following functions. ? programmable interval timer operation ? square wave output of any frequency to the pton pin (n = 0, 1) ? event counter operation ? divides the frequency of signal input via the tin pin to 1-nth of the original signal and outputs the divided frequency to the pton pin (frequency divider operation). ? supplies the shift clock to the serial interface circuit. ? reads the count value. the timer/event counter operates in the following two modes as set by the mode register. table 6-2. operation modes of timer/event counter channel channel 0 channel 1 mode 8-bit timer/event counter mode ?? 16-bit timer/event counter mode ?
m pd754302, 754304, 754302(a), 754304(a) 25 figure 6-4. timer/event counter (channel 0) block diagram port1.3 input buffer ti0/ti1/p13 from clock generator mpx tm05 tm06 tm04 tm03 tm02 tm01 tm00 tm0 8 decoder modulo register (8) comparator (8) count register (8) 8 8 clear 16-bit timer/event counter mode timer operation start timer/event counter (channel 1) tm12 signal (when 16-bit timer/event counter mode) timer/event counter (channel 1) match signal (when 16-bit timer/event counter mode) timer/event counter (channel 1) clear signal (when 16-bit timer/event counter mode) match overflow toe0 bit 2 of pmgb t0 enable flag output buffer p20/pto0 timer/event counter (channel 1) clock input to serial interface intt0 irqt0 set signal irqt0 clear signal reset t0 internal bus cp reset port 2 i/o mode tout f/f 8 port 2.0 p20 output latch tmod0 f x /2 2 f x /2 4 f x /2 6 f x /2 8 f x /2 10
m pd754302, 754304, 754302(a), 754304(a) 26 figure 6-5. timer/event counter (channel 1) block diagram port1.3 input buffer ti0/ti1/p13 timer/event counter (channel 0) output from clock generator mpx e tm16 tm15 tm14 tm13 tm12 tm11 tm10 tm1 decoder 16 bit timer/event counter mode cp timer operation start selector clear 8 8 8 8 modulo register (8) comparator (8) count register (8) timer/event counter (channel 0) match signal/operation start (when 16-bit timer/event counter mode) timer/event counter (channel 0) comparator (when 16-bit timer/event counter mode) t1 tmod1 match tout f/f reset t1 enable flag p21 output latch port 2 input/output mode intt1 irqt1 set signal irqt1 clear signal reset toe1 port2.1 bit 2 of pmgb p21/pto1 output buffer internal bus timer/event counter (channel 0) tm02 signal (when 16 bit timer/event counter mode) f x /2 2 f x /2 6 f x /2 8 f x /2 10 f x /2 12
m pd754302, 754304, 754302(a), 754304(a) 27 6.6 serial interface the m pd754304 incorporates the clocked 8-bit serial interface, and the following three modes are provided. ? operation stop mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode
m pd754302, 754304, 754302(a), 754304(a) 28 figure 6-6. serial interface block diagram p03/si p02/so/sb0 p01/sck 8/4 csim 88 sbic cmdt so latch relt set clr dq (8) f x /2 3 f x /2 4 f x /2 6 8 (8) (8) internal bus slave address register (sva) address comparator matching signal bit test shift register (sio) p01 output iatch serial clock counter serial clock control circuit serial clock selector intcsi control circuit tout f/f (from timer/event counter 0) bit manipulation selector external sck irqcsi set signal intcsi
m pd754302, 754304, 754302(a), 754304(a) 29 6.7 bit sequential buffer ....... 16 bits the bit sequential buffer (bsb) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. the data memory is composed of 16 bits and the pmem.@l addressing of a bit manipulation instruction is possible. the bit can be specified indirectly by the l register. in this case, processing can be done by moving the specified bit in sequence by incrementing and decrementing the l register in the program loop. figure 6-7. bit sequential buffer format address bit symbol l register l = fh l = ch l = bh l = 8h l = 7h l = 4h l = 3h l = 0h decs l incs l bsb3 bsb2 bsb1 bsb0 3210321032103210 fc3h fc2h fc1h fc0h remarks 1. in the pmem.@l addressing, the specified bit moves corresponding to the l register. 2. in the pmem.@l addressing, the bsb can be manipulated regardless of mbe/msb specification.
m pd754302, 754304, 754302(a), 754304(a) 30 7. interrupt function and test function the m pd754304 has seven kinds of interrupt sources and one kind of test source. two types of edge detection testable inputs are provided for int2 of the test source. the interrupt control circuit of the m pd754304 has the following functions. (1) interrupt function ? vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (ie ) and interrupt master enable flag (ime). ? can set any interrupt start address. ? multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (ips). ? test function of interrupt request flag (irq ). an interrupt generated can be checked by software. ? release the standby mode. a release interrupt can be selected by the interrupt enable flag. (2) test function ? test request flag (irqxxx) generation can be checked by software. ? release the standby mode. the test source to be released can be selected by the test enable flag.
m pd754302, 754304, 754302(a), 754304(a) 31 figure 7-1. interrupt control circuit block diagram note noise eliminator (standby release is disabled when noise eliminator is selected.) internal bus interrupt enable flag (ie ) irqbt irq4 irq0 irq1 irqcsi irqt0 irqt1 irq2 intcsi intt0 intt1 both edge detector edge detector edge detector selec- tor int4/p00 int0/p10 int1/p11 int2/p12 kr0/p60 kr7/p73 rising edge detector falling edge detector selec- tor im2 standby release signal priority control circuit vector table address generator decoder ime ips ist0 vrqn note im2 im1 im0 214 intbt ist1
m pd754302, 754304, 754302(a), 754304(a) 32 8. standby function in order to save dissipation power while a program is in a standby mode, two types of standby modes (stop mode and halt mode) are provided for the m pd754304. table 8-1. operation status in standby mode item mode stop mode halt mode set instruction stop instruction halt instruction operation clock generator the system clock stops oscillation. only the cpu clock f halts (oscillation status continues). basic interval timer/ operation stops. operable (the irqbt is set in the watchdog timer reference interval). serial interface operable only when an external sck operable input is selected as the serial clock. timer/event counter operable only when a signal input to operable the ti0 and ti1 pins are specified as the count clock. external interrupt the int1, 2, and 4 are operable. only the int0 is not operated note . cpu the operation stops. release signal interrupt request signal sent from the operable hardware enabled by the interrupt enable flag or reset signal input. note operable only when the noise eliminator is not used (im02 = 1) by bit 2 of the edge detection mode register (im0).
m pd754302, 754304, 754302(a), 754304(a) 33 9. reset function there are two reset inputs: external reset signal and reset signal sent from the basic interval timer/ watchdog timer. when either one of the reset signals are input, an internal reset signal is generated. figure 9-1 shows the circuit diagram of the above two inputs. figure 9-1. configuration of reset function generation of the reset signal initializes each hardware as listed in table 9-1. figure 9-2 shows the timing chart of the reset operation. figure 9-2. reset operation by reset signal generation note the following two times can be selected by the mask option. 2 17 /f x (21.8 ms : @ 6.0 mhz, 31.3 ms: @ 4.19 mhz) 2 15 /f x (5.46 ms : @ 6.0 mhz, 7.81 ms: @ 4.19 mhz) reset internal reset signal reset signal sent from the basic interval timer/watchdog timer wdtm internal bus operation mode or standby mode wait note reset signal generated operation mode halt mode internal reset operation
m pd754302, 754304, 754302(a), 754304(a) 34 table 9-1. status of each hardware after reset (1/2) hardware reset signal generation reset signal generation in the standby mode in operation program counter (pc) m pd754302 sets the low-order 3 bits of sets the low-order 3 bits of program memorys address program memorys address 0000h to the pc10-pc8 and the 0000h to the pc10-pc8 and the contents of address 0001h to contents of address 0001h to the pc7-pc0. the pc7-pc0. m pd754304 sets the low-order 4 bits of sets the low-order 4 bits of program memory's address program memory's address 0000h to the pc11-pc8 and the 0000h to the pc11-pc8 and the contents of address 0001h to contents of address 0001h to the pc7-pc0. the pc7-pc0. psw carry flag (cy) held undefined skip flag (sk0-sk2) 0 0 interrupt status flag (ist0, ist1) 0 0 bank enable flag (mbe, rbe) sets the bit 6 of program sets the bit 6 of program memorys address 0000h to memorys address 0000h to the rbe and bit 7 to the mbe. the rbe and bit 7 to the mbe. stack pointer (sp) undefined undefined stack bank select register (sbs) 1000b 1000b data memory (ram) held undefined general-purpose register (x, a, h, l, d, e, b, c) held undefined bank select register (mbs, rbs) 0, 0 0, 0 basic interval counter (bt) undefined undefined timer/watchdog mode register (btm) 0 0 timer watchdog timer enable flag (wdtm) 00 timer/event counter (t0) 0 0 counter (t0) modulo register (tmod0) ffh ffh mode register (tm0) 0 0 toe0, tout f/f 0, 0 0, 0 timer/event counter (t1) 0 0 counter (t1) modulo register (tmod1) ffh ffh mode register (tm1) 0 0 toe1, tout f/f 0, 0 0, 0 serial shift register (sio) held undefined interface operation mode register (csim) 00 sbi control register (sbic) 0 0 slave address register (sva) held undefined clock generator, processor clock control register (pcc) 00 clock output clock output mode register (clom) 0 0 circuit
m pd754302, 754304, 754302(a), 754304(a) 35 table 9-1. status of each hardware after reset (2/2) hardware reset signal generation reset signal generation in the standby mode in operation interrupt interrupt request flag (irq ) reset (0) reset (0) function interrupt enable flag (ie )0 0 interrupt priority select register (ips) 0 0 int0, 1, 2 mode registers (im0, im1, im2) 0, 0, 0 0, 0, 0 digital port output buffer off off output latch cleared (0) cleared (0) i/o mode registers (pmga, b, c) 0 0 pull-up resistor setting registers (poga, b) 00 bit sequential buffers (bsb0-bsb3) held undefined
m pd754302, 754304, 754302(a), 754304(a) 36 10. mask option the m pd754304 has the following mask options: ? mask option of p50 through p53 pull-up resistors can be connected to these pins. (1) specify connection of a pull-up resistor in 1-bit units. (2) do not specify connection of a pull-up resistor. ? standby function mask option the wait time when the reset signal is input can be selected. (1) 2 17 /f x (21.8 ms: f x = 6.0 mhz, 31.3 ms: f x = 4.19 mhz) (2) 2 15 /f x (5.46 ms: f x = 6.0 mhz, 7.81 ms: f x = 4.19 mhz)
m pd754302, 754304, 754302(a), 754304(a) 37 11. instruction sets (1) expression formats and description methods of operands the operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. for details, refer to ra75x assembler package users manuallanguage (eeu-1363) . if there are several elements, one of them is selected. capital letters and the + and C symbols are key words and are described as they are. for immediate data, appropriate numbers and labels are described. instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. however, there are restrictions in the labels that can be described for fmem and pmem. for details, refer to the m pd754304 users manual (u10123e) . representation description method format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh, ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr 0000h-07ffh immediate data or label ( m pd754302) 0000h-0fffh immediate data or label ( m pd754304) addr1 0000h-07ffh immediate data or label ( m pd754302) 0000h-0fffh immediate data or label ( m pd754304) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (where bit 0 = 0) or label portn port0-port3, port5-port8 ie iebt, iet0, iet1, ie0-ie2, ie4, iecsi rbn rb0-rb3 mbn mb0, mb15 note mem can be only used for even address in 8-bit data processing.
38 m pd754302, 754304, 754302(a), 754304(a) (2) legend in explanation of operation a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : xa register pair; 8-bit accumulator bc : bc register pair de : de register pair hl : hl register pair xa : xa expanded register pair bc : bc expanded register pair de : de expanded register pair hl : hl expanded register pair pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0-3, 5-8) ime : interrupt master enable flag ips : interrupt priority select register iexxx : interrupt enable flag rbs : register bank select register mbs : memory bank select register pcc : processor clock control register . : separation between address and bit ( ) : the contents addressed by h : hexadecimal data
m pd754302, 754304, 754302(a), 754304(a) 39 (3) explanation of symbols under addressing area column *1 mb = mbe?mbs (mbs = 0, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (000h-07fh) mb = 15 (f80h-fffh) data memory addressing mbe = 1 : mb = mbs (mbs = 0, 15) *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 m pd754302 addr = 0000h-07ffh m pd754304 addr = 0000h-0fffh *7 addr = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 addr1 = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 *8 m pd754302 caddr = 0000h-07ffh program memory addressing m pd754304 caddr = 0000h-0fffh (pc 12 = 0) *9 faddr = 0000h-07ffh *10 taddr = 0020h-007fh *11 m pd754302 addr1 = 0000h-07ffh m pd754304 addr1 = 0000h-0fffh remarks 1. mb indicates memory bank that can be accessed. 2. in *2, mb = 0 independently of how mbe and mbs are set. 3. in *4 and *5, mb = 15 independently of how mbe and mbs are set. 4. *6 to *11 indicate the areas that can be addressed. (4) explanation of number of machine cycles column s denotes the number of machine cycles required by skip operation when a skip instruction is executed. the value of s varies as follows. ? when no skip is made: s = 0 ? when the skipped instruction is a 1- or 2-byte instruction: s = 1 ? when the skipped instruction is a 3-byte instruction note : s = 2 note 3-byte instruction: br !addr, bra !addr1, call !addr or calla !addr1 instruction caution the geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle of cpu clock (= t cy ); time can be selected from among four types by setting pcc.
40 m pd754302, 754304, 754302(a), 754304(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area transfer mov a, #n4 1 1 a n4 string effect a reg1, #n4 2 2 reg1 n4 xa, #n8 2 2 xa n8 string effect a hl, #n8 2 2 hl n8 string effect b rp2, #n8 2 2 rp2 n8 a, @hl 1 1 a (hl) *1 a, @hl+ 1 2+s a (hl), then l l+1 *1 l = 0 a, @hlC 1 2+s a (hl), then l lC1 *1 l = fh a, @rpa 1 1 a (rpa) *2 xa, @hl 2 2 xa (hl) *1 @hl, a 1 1 (hl) a*1 @hl, xa 2 2 (hl) xa *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 mem, a 2 2 (mem) a*3 mem, xa 2 2 (mem) xa *3 a, reg1 2 2 a reg1 xa, rp' 2 2 xa rp' reg1, a 2 2 reg1 a rp'1, xa 2 2 rp'1 xa xch a, @hl 1 1 a (hl) *1 a, @hl+ 1 2+s a (hl), then l l+1 *1 l = 0 a, @hlC 1 2+s a (hl), then l lC1 *1 l = fh a, @rpa 1 1 a (rpa) *2 xa, @hl 2 2 xa (hl) *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 a, reg1 1 1 a reg1 xa, rp' 2 2 xa rp' table movt xa, @pcde 1 3 l m pd754302 reference xa (pc 10C8 +de) rom l m pd754304 xa (pc 11C8 +de) rom xa, @pcxa 1 3 l m pd754302 xa (pc 10C8 +xa) rom l m pd754304 xa (pc 11C8 +xa) rom xa, @bcde 1 3 xa (bcde) rom note *6 xa, @bcxa 1 3 xa (bcxa) rom note *6 note to use the m pd754302, clear the most significant bit of the register c and register b to 0. to use the m pd754304, clear the register b to 0.
m pd754302, 754304, 754302(a), 754304(a) 41 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area bit transfer mov1 cy, fmem.bit 2 2 cy (fmem.bit) *4 cy, pmem.@l 2 2 cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy (h+mem 3C0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) cy *4 pmem.@l, cy 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) cy *5 @h+mem.bit, cy 2 2 (h+mem 3C0 .bit) cy *1 operation adds a, #n4 1 1+s a a+n4 carry xa, #n8 2 2+s xa xa+n8 carry a, @hl 1 1+s a a+(hl) *1 carry xa, rp' 2 2+s xa xa+rp' carry rp'1, xa 2 2+s rp'1 rp'1+xa carry addc a, @hl 1 1 a, cy a+(hl)+cy *1 xa, rp' 2 2 xa, cy xa+rp'+cy rp'1, xa 2 2 rp'1, cy rp'1+xa+cy subs a, @hl 1 1+s a aC(hl) *1 borrow xa, rp' 2 2+s xa xaCrp' borrow rp'1, xa 2 2+s rp'1 rp'1Cxa borrow subc a, @hl 1 1 a, cy aC(hl)Ccy *1 xa, rp' 2 2 xa, cy xaCrp'Ccy rp'1, xa 2 2 rp'1, cy rp'1CxaCcy and a, #n4 2 2 a a ? n4 a, @hl 1 1 a a ? (hl) *1 xa, rp' 2 2 xa xa ? rp' rp'1, xa 2 2 rp'1 rp'1 ? xa or a, #n4 2 2 a a M n4 a, @hl 1 1 a a M (hl) *1 xa, rp' 2 2 xa xa M rp' rp'1, xa 2 2 rp'1 rp'1 M xa xor a, #n4 2 2 a a v n4 a, @hl 1 1 a a v (hl) *1 xa, rp' 2 2 xa xa v rp' rp'1, xa 2 2 rp'1 rp'1 v xa accumulator rorc a 1 1 cy a 0 , a 3 cy, a nC1 a n manipulation not a 2 2 a a increment incs reg 1 1+s reg reg+1 reg=0 and rp1 1 1+s rp1 rp1+1 rp1=00h decrement @hl 2 2+s (hl) (hl)+1 *1 (hl)=0 mem 2 2+s (mem) (mem)+1 *3 (mem)=0 decs reg 1 1+s reg regC1 reg=fh rp' 2 2+s rp' rp'C1 rp'=ffh
42 m pd754302, 754304, 754302(a), 754304(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area comparison ske reg, #n4 2 2+s skip if reg = n4 reg=n4 @hl, #n4 2 2+s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1+s skip if a = (hl) *1 a = (hl) xa, @hl 2 2+s skip if xa = (hl) *1 xa = (hl) a, reg 2 2+s skip if a = reg a=reg xa, rp' 2 2+s skip if xa = rp' xa=rp' carry flag set1 cy 1 1 cy 1 manipulation clr1 cy 1 1 cy 0 skt cy 1 1+s skip if cy = 1 cy=1 not1 cy 1 1 cy cy memory bit set1 mem.bit 2 2 (mem.bit) 1*3 manipulation fmem.bit 2 2 (fmem.bit) 1*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) 1*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) 1*1 clr1 mem.bit 2 2 (mem.bit) 0*3 fmem.bit 2 2 (fmem.bit) 0*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) 0*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) 0*1 skt mem.bit 2 2+s skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+s skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=1 *1 (@h+mem.bit)=1 skf mem.bit 2 2+s skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+s skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=0 *5 (pmem.@l)=0 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=0 *1 (@h+mem.bit)=0 sktclr fmem.bit 2 2+s skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 and clear *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=1 and clear *1 (@h+mem.bit)=1 and1 cy, fmem.bit 2 2 cy cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy cy ? (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy ? (h+mem 3C0 .bit) *1 or1 cy, fmem.bit 2 2 cy cy M (fmem.bit) *4 cy, pmem.@l 2 2 cy cy M (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy M (h+mem 3C0 .bit) *1 xor1 cy, fmem.bit 2 2 cy cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy cy v (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy v (h+mem 3C0 .bit) *1
m pd754302, 754304, 754302(a), 754304(a) 43 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch br note addr C C ? m pd754302 *6 pc 10C0 addr select appropriate instruction from among br !addr, brcb !caddr and br $addr according to the assembler being used. ? m pd754304 pc 11C0 addr select appropriate instruction from among br !addr, brcb !caddr and br $addr according to the assembler being used. addr1 C C ? m pd754302 *11 pc 10-0 addr select appropriate instruction from among br !addr, bra !addr1, brcb !caddr and br $addr1 according to the assembler being used. ? m pd754304 pc 11C0 addr1 select appropriate instruction from among br !addr, bra !addr1, brcb !caddr and br $addr1 according to the assembler being used. !addr 3 3 ? m pd754302 *6 pc 10C0 addr ? m pd754304 pc 11C0 addr $addr 1 2 ? m pd754302 *7 pc 10C0 addr ? m pd754304 pc 11C0 addr $addr1 1 2 ? m pd754302 pc 10C0 addr1 ? m pd754304 pc 11C0 addr1 pcde 2 3 ? m pd754302 pc 10C0 pc 10-8 +de ? m pd754304 pc 11C0 pc 11-8 +de pcxa 2 3 ? m pd754302 pc 10C0 pc 10-8 +xa ? m pd754304 pc 11C0 pc 11-8 +xa note the above operations in the double boxes can be performed only in the mk ii mode.
44 m pd754302, 754304, 754302(a), 754304(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch br bcde 2 3 ? m pd754302 *6 pc 10C0 bcde note1 ? m pd754304 pc 11C0 bcde note2 bcxa 2 3 ? m pd754302 *6 pc 10C0 bcxa note1 ? m pd754304 pc 11C0 bcxa note2 bra note3 !addr1 3 3 ? m pd754302 *11 pc 10C0 addr1 ? m pd754304 pc 11C0 addr1 brcb !caddr 2 2 ? m pd754302 *8 pc 10C0 caddr 10C0 ? m pd754304 pc 11C0 caddr 11C0 subroutine calla note3 !addr1 3 3 ? m pd754302 *11 stack control (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 10C0 (spC5) 0, 0, 0, 0 pc 10C0 addr1, sp spC6 ? m pd754304 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 pc 11C0 addr1, sp spC6 call note3 !addr 3 3 ? m pd754302 *6 (spC3) mbe, rbe, 0, 0 (spC4) (spC1) (spC2) pc 10C0 pc 10C0 addr, sp spC4 ? m pd754304 (spC3) mbe, rbe, 0, 0 (spC4) (spC1) (spC2) pc 11C0 pc 11C0 addr, sp spC4 4 ? m pd754302 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 10C0 (spC5) 0, 0, 0, 0 pc 10C0 addr, sp spC6 ? m pd754304 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 pc 11C0 addr, sp spC6 notes 1. 0 must be set to the most significant bit of the register c and register b. 2. 0 must be set to register b. 3. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
m pd754302, 754304, 754302(a), 754304(a) 45 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine callf note !faddr 2 2 ? m pd754302 *9 stack control (spC3) mbe, rbe, 0, 0 (spC4) (spC1) (spC2) pc 10C0 pc 10C0 faddr, sp spC4 ? m pd754304 (spC3) mbe, rbe, 0, 0 (spC4) (spC1) (spC2) pc 11C0 pc 11C0 0+faddr, sp spC4 3 ? m pd754302 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 10C0 (spC5) 0, 0, 0, 0 pc 10C0 faddr, sp spC6 ? m pd754304 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 pc 11C0 0+faddr, sp spC6 ret note 13 ? m pd754302 pc 10C0 (sp) (sp+3) (sp+2) mbe, rbe, 0, 0 (sp+1), sp sp+4 ? m pd754304 pc 11C0 (sp) (sp+3) (sp+2) mbe, rbe, 0, 0 (sp+1), sp sp+4 ? m pd754302 , , mbe, rbe (sp+4) 0, 0, 0, 0, (sp+1) pc 10C0 (sp) (sp+3) (sp+2), sp sp+6 ? m pd754304 , , mbe, rbe (sp+4) 0, 0, 0, 0 (sp+1) pc 10C0 (sp) (sp+3) (sp+2), sp sp+6 rets note 1 3+s ? m pd754302 unconditional mbe, rbe, 0, 0 (sp+1) pc 10C0 (sp) (sp+3) (sp+2) sp sp+4 then skip unconditionally ? m pd754304 mbe, rbe, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 then skip unconditionally note the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
46 m pd754302, 754304, 754302(a), 754304(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine rets note1 1 3+s ? m pd754302 unconditional stack control 0, 0, 0, 0 (sp+1) pc 10C0 (sp) (sp+3) (sp+2) , , mbe, rbe (sp+4) sp sp+6 then skip unconditionally ? m pd754304 0, 0, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) , , mbe, rbe (sp+4) sp sp+6 then skip unconditionally reti note1 13 ? m pd754302 mbe, rbe, 0, 0 (sp+1) pc 10C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 ? m pd754304 mbe, rbe, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 ? m pd754302 0, 0, 0, 0 (sp+1) pc 10C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 ? m pd754304 0, 0, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 push rp 1 1 (spC1)(spC2) rp, sp spC2 bs 2 2 (spC1) mbs, (spC2) rbs, sp spC2 pop rp 1 1 rp (sp+1) (sp), sp sp+2 bs 2 2 mbs (sp+1), rbs (sp), sp sp+2 interrupt ei 2 2 ime (ips.3) 1 control ie 22ie 1 di 2 2 ime (ips.3) 0 ie 22ie 0 input/output in note2 a, portn 2 2 a portn (n = 0-3, 5-8) xa, portn 2 2 xa portn+1, portn (n = 6) out note2 portn, a 2 2 portn a (n = 2, 3, 5-8) portn, xa 2 2 portn+1, portn xa (n = 6) notes 1. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 2. while the in instruction and out instruction are being executed, the mbe must be set to 0 or 1 and mbs must be set to 15.
m pd754302, 754304, 754302(a), 754304(a) 47 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area cpu control halt 2 2 set halt mode (pcc.2 1) stop 2 2 set stop mode (pcc.3 1) nop 1 1 no operation special sel rbn 2 2 rbs n (n = 0-3) mbn 2 2 mbs n (n = 0, 15) geti notes 1, 2 taddr 1 3 ? m pd754302 *10 ? when tbr instruction pc 10C0 (taddr) 2C0 + (taddr+1) ? when tcall instruction (spC4) (spC1) (spC2) pc 10C0 (spC3) mbe, rbe, 0, 0 pc 10C0 (taddr) 2C0 + (taddr+1) sp spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction ? m pd754304 ? when tbr instruction pc 11C0 (taddr) 3C0 + (taddr+1) ? when tcall instruction (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, rbe, 0, 0 pc 11C0 (taddr) 3C0 + (taddr+1) sp spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction 3 ? m pd754302 *10 ? when tbr instruction pc 10C0 (taddr) 2C0 + (taddr+1) 4 ? when tcall instruction (spC6) (spC3) (spC4) pc 10C0 (spC5) 0, 0, 0, 0 (spC2) , , mbe, rbe pc 10C0 (taddr) 2C0 + (taddr+1) sp spC6 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction notes 1. the tbr and tcall instructions are the table definition assembler directives of the geti instruction. 2. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCC CCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCC CCCCCCCCCCCC CCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCC
48 m pd754302, 754304, 754302(a), 754304(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area special geti notes 1, 2 taddr 1 3 ? m pd754304 *10 ? when tbr instruction pc 11C0 (taddr) 3C0 + (taddr+1) 4 ? when tcall instruction (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 (spC2) , , mbe, rbe pc 11C0 (taddr) 3C0 + (taddr+1) sp spC6 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction notes 1. the tbr and tcall instructions are the table definition assembler directives of the geti instruction. 2. the above operations in the double boxes can be performed only in the mk ii mode. CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCC CCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCC CCCCCCCCCCCC
m pd754302, 754304, 754302(a), 754304(a) 49 12. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +7.0 v input voltage v i1 except port 5 C0.3 to v dd + 0.3 v v i2 port 5 pull-up resistor incorporated C0.3 to v dd + 0.3 v n-ch open-drain C0.3 to +14 v output voltage v o C0.3 to v dd + 0.3 v output current, high i oh per pin C10 ma for all pins C30 ma output current, low i ol note per pin 30 ma for all pins 220 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the products. be sure to use the products within the ratings. capacitance (t a = 25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v 15 pf i/o capacitance c io 15 pf
50 m pd754302, 754304, 754302(a), 754304(a) system clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended constant parameter testing conditions min. typ. max. unit ceramic oscillation 1.0 6.0 note2 mhz resonator frequency (f x ) note1 oscillation after v dd reaches min. 4 ms stabilization value of oscillation time note 3 voltage range crystal oscillation 1.0 6.0 note2 mhz resonator frequency(f x ) note1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note3 30 ms external x1 input 1.0 6.0 note2 mhz clock frequency (f x ) note1 x1 input high- and 83.3 500 ns low-level widths (t xh , t xl ) notes 1. only the oscillator characteristics are shown. for the instruction execution time, refer to ac charac- teristics . 2. if the oscillation frequency is 4.19 mhz < f x 6.0 mhz at 1.8 v v dd < 2.7 v, set the processor control register (pcc) to a value other than 0011. if the pcc is set to 0011, the rated cycle time of 0.95 m s is not satisfied. 3. oscillation stabilization time is a time required for oscillation to stabilize after application of v dd , or after the stop mode has been released. caution when using the oscillation circuit of the main system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: ? keep the wire length as short as possible. ? do not cross other signal lines. ? do not route the wiring in the vicinity of lines though which a high fluctuating current flows. ? always keep the ground point of the capacitor of the oscillation circuit as the same potential as v ss . ? do not connect the power source pattern through which a high current flows. ? do not extract signals from the oscillation circuit. x1 x2 x1 x2 c1 c2 x1 x2 c1 c2
m pd754302, 754304, 754302(a), 754304(a) 51 recommended oscillation circuit constants ceramic resonator (t a = C40 to +85 c) manufacturer product frequency recommended circuit constants (pf) oscillation voltage range (v dd ) remarks (mhz) c1 c2 min. max. murata csb1000j note 1.0 100 100 2.7 5.5 rd = 5.6 k w mfg. co., ltd csa2.00mg 2.0 30 30 1.8 5.5 cst2.00mg C C capacitor incorporated csa3.58mg 3.58 30 30 1.8 5.5 cst3.58mgw C C capacitor incorporated csa3.58mgu 30 30 cst3.58mgwu C C capacitor incorporated csa4.00mg 4.0 30 30 2.0 5.5 cst4.00mgw C C capacitor incorporated csa4.00mgu 30 30 1.8 cst4.00mgwu C C capacitor incorporated csa6.00mg 6.0 30 30 2.9 5.5 cst6.00mgw C C capacitor incorporated csa6.00mgu 30 30 1.8 cst6.00mgwu C C capacitor incorporated kyocera corp. kbr-1000f/y 1.0 100 100 1.8 5.5 t a = C20 to +80 c kbr-2.0ms 2.0 47 47 2.0 5.5 kbr-4.0msa 4.0 33 33 1.8 5.5 kbr-4.0mks C C capacitor incorporated, t a = C20 to +80 c pbrc 4.00a 33 33 t a = C20 to +80 c pbrc 4.00b C C capacitor incorporated, t a = C20 to +80 c kbr-6.0msa 6.0 33 33 1.8 5.5 t a = C20 to +80 c pbrc 6.00a pbrc 6.00b C C capacitor incorporated, t a = C20 to +80 c tdk ccr1000k2 1.0 100 100 1.8 5.5 ccr2.0mc33 2.0 C C capacitor incorporated ccr4.19mc3 4.19 fcr4.19mc5 ccr6.0mc3 6.0
52 m pd754302, 754304, 754302(a), 754304(a) note if using muratas csb1000j (1.0 mhz) as the ceramic resonator, a limited resistor (rd = 5.6 k w ) is required (see figure below). if using any other recommended resonator, no limited resistor is needed. caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. if oscillation frequency accu- racy is required for actual circuits, it is necessary to adjust the oscillation frequency of the resonator in the circuit. please inquire directly to the maker of the resonator for data as needed. x1 x2 c1 c2 rd csb1000j
m pd754302, 754304, 754302(a), 754304(a) 53 dc characteristics (t a = C40 to + 85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit output current, low i ol per pin 15 ma for all pins 150 ma input voltage, high v ih1 ports 2, 3, 8 2.7 v v dd 5.5 v 0.7 v dd v dd v 1.8 v v dd <2.7 v 0.9 v dd v dd v v ih2 ports 0, 1, 6, 7, reset 2.7 v v dd 5.5 v 0.8 v dd v dd v 1.8 v v dd <2.7 v 0.9 v dd v dd v v ih3 port 5 pull-up resistor 2.7 v v dd 5.5 v 0.7 v dd v dd v incorporated 1.8 v v dd <2.7 v 0.9 v dd v dd v n-ch open drain 2.7 v v dd 5.5 v 0.7 v dd 13 v 1.8 v v dd <2.7 v 0.9 v dd 13 v v ih4 x1 v dd C0.1 v dd v input voltage, low v il1 ports 2, 3, 5, 8 2.7 v v dd 5.5 v 0 0.3 v dd v 1.8 v v dd <2.7 v 0 0.1 v dd v v il2 ports 0, 1, 6, 7, reset 2.7 v v dd 5.5 v 0 0.2 v dd v 1.8 v v dd <2.7 v 0 0.1 v dd v v il3 x1 0 0.1 v output voltage, high v oh sck, so, ports 2, 3, 6, 7, 8 i oh = C1 ma v dd C0.5 v output voltage, low v ol1 sck, so, ports 2, 3, 5, 6, 7, 8 i ol = 15 ma 0.2 2.0 v v dd = 5 v 10% i ol = 1.6 ma 0.4 v v ol2 sb0 n-ch open-drain pull-up resistor 1 k w 0.2 v dd v input leak current, high i lih1 v i = v dd pins other than x1 3 m a i lih2 x1 20 m a i lih3 v i = 13 v port 5 (n-ch open drain) 20 m a input leak current, low i lil1 v i = 0 v pins other than x1 and port 5 C3 m a i lil2 x1 C20 m a i lil3 port 5 (n-ch open drain) C3 m a other than input instruction execution time port 5 (n-ch open drain) input C30 m a input instruction execution time C10 C27 m a C3 C8 m a output leak current, high i loh1 v o = v dd sck, so/sb0, ports 2, 3, 6, 7, 8, 3 m a port 5 (with on-chip pull-up resistor) i loh2 v o = 13 v port 5 (n-ch open drain) 20 m a output leak current, low i lol v o = 0 v C3 m a on-chip pull-up resistor r l1 v i = 0 v ports 0 to 3 and 6 to 8 (except p00 pin) 50 100 200 k w r l2 port 5 15 30 60 k w
54 m pd754302, 754304, 754302(a), 754304(a) dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit supply current note1 i dd1 6.00 mhz v dd = 5.0 v 10% note2 1.50 5.00 ma crystal resonator v dd = 3.0 v 10% note3 0.33 1.00 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.61 1.85 ma v dd = 3.0 v 10% 0.24 0.75 ma i dd1 4.19 mhz v dd = 5.0 v 10% note2 1.20 3.50 ma crystal resonator v dd = 3.0 v 10% note3 0.17 0.55 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.40 1.50 ma v dd = 3.0 v 10% 0.13 0.50 ma i dd5 stop mode v dd = 5.0 v 10% 0.05 10.0 m a v dd = 3.0 v 10% 0.02 5.00 m a t a = 25 c 0.02 3.00 m a notes 1. does not include current fed to on-chip pull-up resistor. 2. when processor clock control register (pcc) is set to 0011, during high-speed mode. 3. when pcc is set to 0000, during low-speed mode.
m pd754302, 754304, 754302(a), 754304(a) 55 ac characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cpu clock cycle time note1 t cy when system v dd = 2.7 to 5.5 v 0.67 64 m s (minimum instruction execution clock is used time = 1 machine cycle) 0.95 64 m s ti0, ti1 input frequency f ti v dd = 2.7 to 5.5 v 0 1 mhz 0 275 khz ti0, ti1 input high- and t tih , t til v dd = 2.7 to 5.5 v 0.48 m s low-level width 1.8 m s interrupt input high- and t inth , t intl int0 im02 = 0 note 2 m s low-level width im02 = 1 10 m s int1, 2, 4 10 m s kr0-7 10 m s reset low-level width t rsl 10 m s notes 1. the cpu clock ( f ) cycle time (minimum instruction execution time) is determined by the ocillation frequency of the con- nected resonator and the processor clock control register (pcc). the figure on the right shows the cycle time t cy characteristics against the supply voltage v dd when the system clock is used. 2. 2t cy or 128/fx depending on the setting of the interrupt mode register (im0). 0.5 01 2 3 4 5 6 1 2 3 4 5 6 60 64 supply voltage v dd [v] (during system clock operation) t cy vs v dd operation guaranteed range cycle time t cy [ s] m
56 m pd754302, 754304, 754302(a), 754304(a) serial transfer operation 2-wire and 3-wire serial i/o mode (sck...internal clock output) (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high- and t kl1 ,v dd = 2.7 to 5.5 v t kcy1 /2C50 ns low-level width t kh1 t kcy1 /2C150 ns si note1 setup time t sik1 v dd = 2.7 to 5.5 v 150 ns (to sck ) 500 ns si note1 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (from sck ) 600 ns sck ?? so note1 t kso1 r = 1 k w , c = 100 pf note2 v dd = 2.7 to 5.5 v 0 250 ns output delay time 0 1000 ns notes 1. sb0 in the 2-wire serial i/o mode. 2. r and c are the load resistance and load capacitance of the so output line. 2-wire and 3-wire serial i/o mode (sck...external clock input) (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high- and t kl2 ,v dd = 2.7 to 5.5 v 400 ns low-level width t kh2 1600 ns si note1 setup time t sik2 v dd = 2.7 to 5.5 v 100 ns (to sck ) 150 ns si note1 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (from sck ) 600 ns sck ?? so note1 t kso2 r = 1 k w , c = 100 pf note2 v dd = 2.7 to 5.5 v 0 300 ns output delay time 0 1000 ns notes 1. sb0 in the 2-wire serial i/o mode. 2. r and c are the load resistance and load capacitance of the so output line.
m pd754302, 754304, 754302(a), 754304(a) 57 ac timing test points (excluding x1 input) note for the values, refer to the dc characteristics . clock timing ti0, ti1 timing t xl t xh 1/f x v dd C 0.1 v 0.1 v x1 input ti0, ti1 t til t tih 1/f ti v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.)
58 m pd754302, 754304, 754302(a), 754304(a) so si sck t kso1, 2 t sik1, 2 t ksi1, 2 t kl1, 2 t kh1, 2 t kcy1, 2 input data output data sck sb0 t kso1, 2 t sik1, 2 t ksi1, 2 t kl1, 2 t kh1, 2 t kcy1, 2 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode
m pd754302, 754304, 754302(a), 754304(a) 59 interrupt input timing reset input timing data memory stop mode low-supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit release signal set time t srel 0 m s oscillation stabilization t wait release by reset note2 ms wait time note1 release by interrupt request note3 ms notes 1. the oscillation stabilization wait time is the time during which the cpu operation is stopped to avoid unstable operation at oscillation start. 2. 2 17 /fx and 2 15 /fx can be selected with mask option. 3. depends on setting of basic interval timer mode register (btm) (see table below). btm3 btm2 btm1 btm0 wait time when f x = 4.19 mhz when f x = 6.0 mhz C0002 20 /f x (approx. 250 ms) 2 20 /f x (approx. 175 ms) C0112 17 /f x (approx. 31.3 ms) 2 17 /f x (approx. 21.8 ms) C1012 15 /f x (approx. 7.81 ms) 2 15 /f x (approx. 5.46 ms) C1112 13 /f x (approx. 1.95 ms) 2 13 /f x (approx. 1.37 ms) int0,1,2,4 kr0-7 t intl t inth reset t rsl
60 m pd754302, 754304, 754302(a), 754304(a) data retention timing (on releasing stop mode by reset) data retention timing (standby release signal: on releasing stop mode by interrupt signal) stop mode data retention mode execution of stop instruction v dddr t wait t srel halt mode operation mode v dd reset internal reset operation stop mode data retention mode execution of stop instruction v dd standby release signal (interrupt request) v dddr t wait t srel halt mode operation mode
m pd754302, 754304, 754302(a), 754304(a) 61 13. characteristics curves (reference values) i dd vs v dd (system clock: 6.0-mhz crystal resonator) 012345678 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 x1 x2 6.0 mhz 22 pf 22 pf pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 halt mode system clock crystal resonator supply voltage v dd (v) supply current i dd (ma) (t a = 25 c)
62 m pd754302, 754304, 754302(a), 754304(a) 012345678 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 system clock halt mode x1 x2 4.19 mhz 22 pf 22 pf pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 crystal resonator supply voltage v dd (v) supply current i dd (ma) (t a = 25 c) i dd vs v dd (system clock: 4.19-mhz crystal resonator)
m pd754302, 754304, 754302(a), 754304(a) 63 14. package drawing 36 pin plastic shrink sop (300 mil) b e l k f g i h j a 1 18 19 36 detail of lead end 55? m m d n p36gm-80-300b-3 item millimeters inches a b c d e f g h i j k 15.54 max. 0.8 (t.p.) 1.8 max. 1.55 7.7 0.3 0.97 max. 0.612 max. 0.005 0.003 0.071 max. 0.303 0.012 0.220 0.039 max. note l m 0.10 0.6 0.2 1.1 5.6 0.004 0.024 +0.008 ?.009 each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 0.043 0.061 0.031 (t.p.) 0.20 +0.10 ?.05 0.008 +0.004 ?.002 n 0.10 0.004 0.014 +0.004 ?.003 0.35 0.125 0.075 +0.10 ?.05 c
64 m pd754302, 754304, 754302(a), 754304(a) 15. recommended soldering conditions the m pd754304 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 15-1. surface mounting type soldering conditions m pd754302gs- : 36-pin plastic shrink sop (300 mil, 0.8-mm pitch) m pd754304gs- : 36-pin plastic shrink sop (300 mil, 0.8-mm pitch) m pd754302gs(a)- : 36-pin plastic shrink sop (300 mil, 0.8-mm pitch) m pd754304gs(a)- : 36-pin plastic shrink sop (300 mil, 0.8-mm pitch) soldering method soldering conditions symbol infrared rays reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-00-2 count: twice or less vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-00-2 count: twice or less wave soldering solder temperature: 260 c or below, time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c or below, time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating).
m pd754302, 754304, 754302(a), 754304(a) 65 appendix a. comparison of functions among m pd750004, 754304, and 75p4308 item m pd750004 m pd754304 m pd75p4308 program memory mask rom mask rom one-time prom 0000h-0fffh 0000h-0fffh 0000h-1fffh (4096 8 bits) (4096 8 bits) (8192 8 bits) data memory 000h-1ffh (512 4 bits) 000h-0ffh (256 4 bits) cpu 75xl cpu instruction w/main system clock ? 0.67, 1.33, 2.67, or 10.7 m s (at 6.0 mhz) execution ? 0.95, 1.91, 3.81, or 15.3 m s (at 4.19 mhz) time w/subsystem clock ? 122 m s (at 32.768 khz) no subsystem clock i/o port cmos input 8 (of which 7 can be connected with on-chip pull-up resistor via software) cmos i/o 18 (on-chip pull-up resistor can be connected via software) n-ch open-drain i/o 8 (pull-up resistor can be 4 (pull-up resistor can be 4 (no mask option) (withstand 13 v) connected by mask option) connected by mask option) total 34 30 (no port 4 pins) timer 4 channels 3 channels ? basic interval timer/ ? basic interval timer/watchdog timer watchdog timer ? 8-bit timer/event counter 0 (f x /2 2 added) ? 8-bit timer/event counter ? 8-bit timer/event counter 1 (ti1, f x /2 2 added) ? 8-bit timer (can be used as 16-bit timer/event counter) ? watch timer clock output (pcl) ? f , 524, 262, or 65.5 khz (main system clock: 4.19 mhz) ? f , 750, 375, or 93.8 khz (main system clock: 6.0 mhz) buz output provided none serial interface 3 modes are supported 2 modes are supported ? 3-wire serial i/o mode ? 3-wire serial i/o mode msb/lsb first selectable msb/lsb first ? 2-wire serial i/o mode selectable ? 2-wire serial i/o mode ? sbi mode watch mode register (wm) provided none system clock control register (scc) suboscillation circuit control register (sos) mbs register mb0, 1 mb0 only stack area (sbs1, 0)
66 m pd754302, 754304, 754302(a), 754304(a) item m pd750004 m pd754304 m pd75p4308 tm0, 1 registers bits 0, 1, and 7 are C fixed to 0 vectored interrupt external: 3, internal: 4 test input external: 1, internal: 1 external: 1 test enable flag (iew) provided none test request flag (irqw) supply voltage v dd = 2.2 to 5.5 v v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85 ?c package ? 42-pin plastic ? 36-pin plastic shrink sop shrink dip (600 mil) (300 mil, 0.8-mm pitch) ? 44-pin plastic qfp (10 10 mm)
m pd754302, 754304, 754302(a), 754304(a) 67 appendix b. development tools the following development tools are available for development of application systems using the m pd754304. in the 75xl series, a common relocatable assembler is used in combination with a device file dedicated to each model. language processor ra75x relocatable assembler host machine order code os supply media (part number) pc-9800 series ms-dos tm 3.5 2hd m s5a13ra75x ver. 3.30 to 5 2hd m s5a10ra75x ver. 6.2 note ibm pc/at tm or refer to 3.5 2hc m s7b13ra75x compatible machine os for ibm pc 5 2hc m s7b10ra75x device file host machine order code os supply media (part number) pc-9800 series ms-dos 3.5 2hd m s5a13df754304 ver. 3.30 to 5 2hd m s5a10df754304 ver. 6.2 note ibm pc/at or refer to 3.5 2hc m s7b13df754304 compatible machine os for ibm pc 5 2hc m s7b10df754304 prom writing tools hardware pg-1500 the pg-1500 is a prom programmer that can program prom-contained single-chip microcontrollers in the standalone mode or under control of a host machine, when connected with an accessory board and an optional programmer adapter. it can also program representative proms including 256k-bit to 4m-bit models. pa-75p4308gs this is a prom programmer adapter dedicated to the m pd75p4308gs and connected to the pg-1500. software pg-1500 controller this connects the pg-1500 and a host machine with a serial or parallel interface to control the pg-1500 from the host machine. host machine order code os supply media (part number) pc-9800 series ms-dos 3.5 2hd m s5a13pg1500 ver. 3.30 to 5 2hd m s5a10pg1500 ver. 6.2 note ibm pc/at or refer to 3.5 2hd m s7b13pg1500 compatible machine os for ibm pc 5 2hc m s7b10pg1500 note although ver.5.00 and later have a task swap function, this function cannot be used with this software. remark the operation of the assembler, device file and pg-1500 controller is guaranteed only on the above host machine and os.
68 m pd754302, 754304, 754302(a), 754304(a) debugging tools the in-circuit emulators (ie-75000-r and ie-75001-r) are available as the program debugging tool for the m pd754304. the system configurations are described as follows. hardware ie-75000-r note 1 in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd754304 subseries, the emulation board ie-75300-r-em and emulation probe that are sold separately must be used with the ie-75000-r. by connecting with the host machine and the prom programmer, efficient debugging can be made. it contains the emulation board ie-75000-r-em which is connected. ie-75001-r in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd754304 subseries, the emulation board ie-75300-r-em and emulation probe which are sold separately must be used with the ie-75001-r. it can debug the system efficiently by connecting the host machine and prom program- mer. ie-75300-r-em emulation board for evaluating the application systems that use a m pd754304 subseries. it must be used with the ie-75000-r or ie-75001-r. ep-754304gs-r emulation probe for the m pd754304gs. it must be connected to ie-75000-r (or ie-75001-r) and ie-75300-r-em. it is supplied with the flexible board ev-9500gs-36 which facilitates connection to a ev-9500gs-36 target system. software ie control program connects the ie-75000-r or ie-75001-r to a host machine via rs-232-c and centronix i/f and controls the ie-75000-r or ie-75001-r on a host machine. host machine order code os supply media (part number) pc-9800 series ms-dos 3.5 2hd m s5a13ie75x ver. 3.30 to 5 2hd m s5a10ie75x ver. 6.2 note 2 ibm pc/at or refer to 3.5 2hc m s7b13ie75x compatible machine os for ibm pc 5 2hc m s7b10ie75x notes 1. maintenance parts 2. although ver.5.00 and later have a task swap function, this function cannot be used with this software. remark operation of the ie control program is guaranteed only on the above host machines and oss.
m pd754302, 754304, 754302(a), 754304(a) 69 os for ibm pc the following ibm pc oss are supported. os version pc dos tm ver. 5.02 to ver. 6.3 j6.1/v note to j6.3/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note ibm dos tm j5.02/v note note only english version is supported. caution ver. 5.0 and later have the task swap function, but this function cannot be used for this software.
70 m pd754302, 754304, 754302(a), 754304(a) appendix c. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device related documents document name document number japanese english m pd754302, 754304 data sheet u10797j this document m pd75p4308 data sheet u10909j u10909e m pd754304 users manual u10123j u10123e m pd754304 instruction table iem-5605 75xl series selection guide u10453j u10453e development tool related documents document name document number japanese english hardware ie-75000-r/ie-75001-r user's manual eeu-846 eeu-1416 ie-75300-r-em user's manual u11354j eeu-1493 ep-754304gs-r user's manual u10677j u10677e pg-1500 user's manual eeu-651 eeu-1335 software ra75x assembler package user's manual operation eeu-731 eeu-1346 language eeu-730 eeu-1363 pg-1500 controller user's manual pc-9800 series eeu-704 eeu-1291 (ms-dos) base pc-9800 series eeu-5008 u10540e (pc dos) base other related documents document name document number japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j iei-1209 nec semiconductor device reliability/quality control system c10983j c10983e static electricity discharge (esd) test mem-539 C guide to quality assurance for semiconductor devices mei-603 mei-1202 microcomputer related product guide - other manufacturers mei-604 C caution these documents are subject to change without notice. be sure to read the latest documents.
m pd754302, 754304, 754302(a), 754304(a) 71 [memo]
72 m pd754302, 754304, 754302(a), 754304(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd754302, 754304, 754302(a), 754304(a) 73 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
74 m pd754302, 754304, 754302(a), 754304(a) no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ms-dos is a trademark of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of ibm corporation.

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